1. Field of the Invention
The present invention relates to a valid technique which is applied to a memory device of multivalued information in a nonvolatile semiconductor memory device and, more particularly, to a valid technique which is applied to a nonvolatile semiconductor memory device (simply referred to as a flash memory) in which a plurality of storage information can be electrically erased all at once.
2. Description of the Prior Art
A flash memory uses nonvolatile memory elements having a control gate and a floating gate for a memory cell which can comprise one transistor. Hitherto, as for the flash memory according to a method of injecting electrons in the floating gate, there are known a flash memory using a tunnel current which is supplied to the floating gate and a flash memory using hot electrons, etc.
An operation for injecting electrons in the floating gate and setting a threshold voltage of the memory cell to the high level is called as xe2x80x9cwritexe2x80x9d and an operation for emitting electrons from the floating gate and setting the threshold voltage of the memory cell to the low level is called as xe2x80x9cerasexe2x80x9d.
According to the writing operation using the tunnel current, a drain area of the nonvolatile memory elements, a source area thereof, and a word line to which a control gate CG is connected are set to auxiliarily 0 V, 0 V, and 17 V, respectively, as shown in FIG. 5A. The tunnel current injects electrons in a floating gate FG and the threshold voltage is set to the high level (logic xe2x80x9c1xe2x80x9d). In this case, in the memory cells not to be written (nonselected cell) which are connected to the same word line, a drain area thereof and a source area thereof are set to auxiliarily 5 V and 5 V, respectively. Thereby, the writing is prevented without generating the tunnel current. Referring to FIG. 5A, the left side of the diagonal line of 17/0 V for example denotes an applied voltage to a selected cell (in this case, the voltage of 17 V is applied to the control gate CG of the selected cell) and the right side thereof (in this case, the voltage of 0 V is applied to the control gate CG of the nonselected cell) denotes an applied voltage to the nonselected memory cell. In the other figures, applied voltages to the selected/nonselected cell are also shown.
On the other hand, according to the writing operation using the hot electrons, a drain area of the nonvolatile memory elements, a source area thereof, and a word line to which the control gate CG is connected are set to auxiliarily 5 V, 0 V, and 10 V, respectively, as shown in FIG. 5B. The hot electrons which are generated in a high electric-field area of a channel are injected in the floating gate FG and the threshold voltage is set to the high level (logic xe2x80x9c1xe2x80x9d) In this case, in the memory cell not to be written (nonselected cell) which are connected to the same word line, a drain area thereof and a source area thereof are set to auxiliarily 0 V. Thereby, a current is prevented from flowing in the memory cell. That is, the hot electrons are prevented to be generated, thereby preventing the writing.
In the erasing operation, when the above-mentioned writing using the tunnel current and the writing using hot electrons are performed, a drain area, a source area, a word line to which the control gate CG is connected are set to auxiliarily 0 V, 0 V, and xe2x88x9217 V, respectively, as shown in FIG. 6. Thereby, electrons are emitted from a floating gate FG and the threshold voltage is set to the low level (logic xe2x80x9c0xe2x80x9d).
Accordingly, one-bit data is stored in one memory cell.
Then, data of two or more bits is stored in one memory cell so as to increase a memory capacity and this proposed concept is generally called as a xe2x80x9cmultivaluedxe2x80x9d memory. Conventional arts of the multivalued memory are disclosed, and ones in Japanese Patent Laid-Open Nos. 10-241380 and 10-27486 are labeled as a first conventional art and a second conventional art, respectively, hereinlater.
Herein, a description is given to a writing sequence, a time for writing, and an influence of word line disturbance which is caused by the writing when the writing using the tunnel current is described as an example in each of the cases according to the first conventional art and the second conventional art in the flash memory in which four-valued data can be stored in one memory cell by use of four threshold-voltages. It is assumed hereinafter that data corresponding to the four of the threshold voltage which is stored in the memory cell is labeled as follows, i.e., data which is in the erased state is labeled as xe2x80x9c00xe2x80x9d and data which is in the writing state is sequentially labeled as xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d in order of the data of the threshold voltage nearer the erased state.
According to the first conventional art, if simultaneous writing data has xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d in the writing starting from the erased state, the writing is executed at three steps of write #1, write #2, and write #3 as shown in FIGS. 3B to 3D.
A description is given to the sequence of the writing operation according to the first conventional art hereinlater with reference to FIGS. 3A to 3E.
Incidentally, in the figures, a table shows write target data, memory cell data, disturbed state of the data which is written in the memory cells corresponding to four adjacent memory cells which are connected to the word line. Here, xe2x80x9c++xe2x80x9d shown in a column of the disturbed state denotes the word line disturbance by the writing of data having a threshold voltage higher than the threshold voltages which the memory cells have, and although not shown, xe2x80x9c+xe2x80x9d denotes the word line disturbance by the writing of data having a threshold voltage lower than the threshold voltages which the memory cells have (reference numerals in FIGS. 1B to 1D, FIGS. 2B to 2D, and FIGS. 4B to 4D are the same as the foregoing).
First of all, in the initial state in FIG. 3A, all of the memory cells which become the write target are set to the erased state (storing data xe2x80x9c00xe2x80x9d) prior to the writing. A word line voltage Vw0 is 0 V.
Next, in write #1 in FIG. 3B, a word-line voltage is Vw1, and the data xe2x80x9c01xe2x80x9d is written to the memory cells to which the data xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d is to be written. In this case, as shown in the figure, the drain voltage and the source voltage which are applied to the memory cells that become the selected cells when the writing is performed are 0 V, and the drain voltage and the source voltage which are applied to the memory cell that becomes the nonselected cell when the writing is performed are 5 V. This is the same hereinbelow.
Sequentially, in write #2 in FIG. 3C, a word line voltage is Vw2 and the data xe2x80x9c10xe2x80x9d is written to the memory cell to which the data xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d is to be written.
Finally, in write #3 in FIG. 3D, a word line voltage is Vw3, and the data xe2x80x9c11xe2x80x9d is written to the memory cell to which the data xe2x80x9c11xe2x80x9d is to be written.
That is, as shown in FIG. 3E, this is a writing method whereby voltages are sequentially applied to the writing data xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d, in other words, from the low word-line voltage Vw0 to the high word-line voltage Vw3 in order of the steps of write #1 to write #3 so that the threshold voltages of the memory cells are set in distribution of the writing data xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d which is write target data for the threshold voltages. Incidentally, in the FIG. 3E, Vwv0 to Vwv3 are word line voltages (threshold voltages) when verification is performed.
According to the second conventional art, the writing is executed at three steps shown in FIGS. 4B to 4D.
A description is given to the sequence of the writing operation according to the second conventional art hereinafter with reference to FIGS. 4A to 4E.
Incidentally, according to the second conventional art, the drain voltage and the source voltage which are applied to the memory cell that becomes the selected cell when the writing is performed are 0 V and the drain voltage and the source voltage which are applied to the memory cell that becomes the nonselected cell when the writing is performed are 5 V.
To start with, in the initial state in FIG. 4A, all of the memory cells which become the write targets are set to the erased state (storing data xe2x80x9c00xe2x80x9d) prior to the writing. A word line voltage Vw0 is 0 V.
Next, in write #1 in FIG. 4B, a word-line voltage is Vw3, and the data xe2x80x9c11xe2x80x9d is written to the memory cell to which the data xe2x80x9c11xe2x80x9d is to be written.
Sequentially, in write #2 in FIG. 4C, a word line voltage is Vw2 and the data xe2x80x9c10xe2x80x9d is written to the memory cell to which the data xe2x80x9c10xe2x80x9d is to be written.
Finally, in write #3 in FIG. 4D, a word line voltage is Vw1 and the data xe2x80x9c01xe2x80x9d is written to the memory cell to which the data xe2x80x9c01xe2x80x9d is to be written.
That is, as shown in FIG. 4E, this is a writing method whereby voltages are sequentially applied to the writing data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c01xe2x80x9d, in other words, from the high word-line voltage Vw3 to the low word-line voltage Vw1 in order of the steps of the write #1 to the write #3 so that the threshold voltages of the memory cells are set in distribution of the writing data xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d which is write target data for the threshold voltages. Incidentally, in the FIG. 4E, Vwv0 to Vwv3 are word-line voltages (threshold voltages) when the verification is performed.
In the writing operation of a general two-valued flash memory, it is necessary to apply the writing voltage until the memory cell whose threshold voltage increases most slowly among the memory cells which are writing-selected cells reaches a predetermined threshold voltage. However, in the multivalued memory, it is necessary to set the memory cell to which the writing already has ended to the writing-nonselected cell not so as to make the discrimination between the writing data and the data corresponding to a further higher threshold voltage impossible by the over writing.
Thus, the writing voltage is applied by use of a pulse and it is necessary to check to see if the threshold voltage of the cell increases up to a target value during the writing pulse (verification). By repeating the applying operation of the writing pulse and the verification for the writing, the threshold voltage is controlled with high precision and, thus realizing the multivalued memory.
According to the writing method of the first conventional art (disclosed in Japanese Patent Laid-Open No. 10-241380) and the second conventional art (disclosed in Japanese Patent Laid-Open No. 10-27486), simultaneous writing is performed to a plurality of memory cells on the same word line and, therein, a writing-selected memory cell and a writing-nonselected memory cell exist in accordance with the data which is written on the memory cell. In the above-mentioned simultaneous writing, it is known that there is a danger in that a high voltage is also applied to the writing-nonselected memory cell in accordance with the writing to the memory cells whose word lines are common, and weak writing occur to the writing-nonselected memory cell (the word line disturbance), thereby fluctuating the threshold voltage and also changing the storing data.
Since a time of xcexc tens seconds is necessary to execute the aforementioned verification for the writing once, it is important to decrease the number of times of the verification so that the writing becomes fast.
However, no problem causes because no data corresponding to the further higher threshold voltage exists in the writing of the data xe2x80x9c11xe2x80x9d in the case of over writing. Then, it is possible for the writing of the data xe2x80x9c11xe2x80x9d to reduce a necessary number of verification times by the writing by use of the high word-line voltage or a pulse having a long applying time.
According to the writing by the tunnel current, as one data whose threshold voltage is more remote from the erased state is written, the quantity of word line disturbance which affects the memory cell at the threshold voltage indicative of another data is larger, and as one data whose threshold voltage is nearer the erased state is written, the influence of the word line disturbance is larger in the writing of another data.
According to the first conventional art, all of the word line disturbance of which affects the memory cells having the data are caused when the data having the higher threshold voltage is written, so that the influence by the word line disturbance is large. Thus, when the data xe2x80x9c11xe2x80x9d is writing (write #3 in FIG. 3D), the influence by the word line disturbance becomes further noticeable if using the higher voltage or the pulse having the long applying time.
According to the second conventional art, the data xe2x80x9c11xe2x80x9d is written prior to the writing of the data xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d, so that no problem of the word line disturbance causes if using the higher voltage or the pulse having the long applying time for the writing of the data xe2x80x9c11xe2x80x9d (write #1 in FIG. 4B). However, according to the writing method of the second conventional art, the time which the writing requires is long because the writing of the data is executed starting from the erased state.
As described above, according to the conventional arts, it is difficult to realize both the decrease in the word line disturbance and the fast operation of the writing.
It is an object of the present invention to provide a writing method of a multivalued-type nonvolatile semiconductor memory device in which the influence by the word line disturbance is small and the fast writing is realized.
The typical essentials of the preset invention to be disclosed are described in the following.
That is, there is provided a writing method of a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages comprising the steps of writing data having one threshold voltage which is the remotest from the erased state prior to the writing data having another threshold voltage, sequentially writing the data having the other threshold voltages starting from data having the threshold voltage which is nearer the erased state, and simultaneously writing data having the threshold voltage which is remote from the erased state to the memory cell.
According to the writing method, it is possible to decrease the influence by the word line disturbance which affects the memory cell which has the threshold voltage that is near the erased state and is apt to be affected by the influence of the word line disturbance. Also, according to the writing method, it is possible to reduce a time which the writing of the data having the threshold voltage that is remote from the erased state requires and to realize the fast writing.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.